Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

• Published in: IEEE transactions on electron devices 2006-05, Vol.53 (5), p.1080-1087
• Main Authors: Gili, E., Kunz, V.D., Uchino, T., Hakim, M.M.A., de Groot, C.H., Ashburn, P., Hall, S.
• Format: Article
• Language: English
• Subjects: Applied sciences; Asymmetry; Band-to-band tunneling; body leakage; Devices; Drains; Electrical junctions; Electronics; Exact sciences and technology; fillet local oxidation (FILOX); gate-induced drain leakage (GIDL); Gates; Ion implantation; Leakage; Leakage current; Leakage currents; Microelectronic fabrication (materials and surfaces technology); MOSFETs; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; Tunneling; vertical MOSFET
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2006.872361

Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from -50 to 200/spl deg/C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain-body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical pillar sidewalls and the horizontal wafer surface.