Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance

• Published in: IEEE transactions on microwave theory and techniques 2006-01, Vol.54 (1), p.31-39
• Main Authors: Mei-Chao Yeh, Zuo-Min Tsai, Ren-Chieh Liu, Lin, K.-Y., Ying-Tang Chang, Wang, Huei
• Format: Article
• Language: English
• Subjects: Body-floating technique; Circuit topology; CMOS process; complementary metal-oxide semiconductor (CMOS) switches; Insertion loss; Loss measurement; MOS devices; nonlinear model; Performance analysis; Power semiconductor switches; Semiconductor device measurement; Semiconductors; single-pole double-throw (SPDT); Standards development; Studies; Wireless LAN
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2005.860894

A low insertion-loss single-pole double-throw switch in a standard 0.18-/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P/sub 1dB/, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P/sub 1dB/ of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P/sub 1dB/ of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm/sup 2/. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.