Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec

This paper investigates the algorithmic complexity of rate distortion optimization and arithmetic coding in the new H.264 video coding standard and proposes a hardware accelerator to reduce it by more than an order of magnitude. The accelerator incorporates arithmetic coding and decoding engines and...

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Bibliographic Details
Published in:IEEE transactions on consumer electronics 2006-05, Vol.52 (2), p.590-597
Main Authors: Nunez-Yanez, Y.L., Chouliaras, V.A., Alfonso, D., Rovati, F.S.
Format: Article
Language:English
Subjects:
Accelerators
Algorithms
Arithmetic
Arithmetic coding
Coding
Decoding
Distortion
Electronics
Engines
Hardware
Instruction sets
Optimization
Rate-distortion
Reduced instruction set computing
Streaming media
Video codecs
Video coding
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Summary:This paper investigates the algorithmic complexity of rate distortion optimization and arithmetic coding in the new H.264 video coding standard and proposes a hardware accelerator to reduce it by more than an order of magnitude. The accelerator incorporates arithmetic coding and decoding engines and efficiently handles all the context information required by RDO and CABAC in H.264. The bit stream generated by the hardware is equivalent to that generated by the JM 9.4 reference implementation. The ISA of a controlling scalar 32-bit RISC CPU has been extended with custom RDO/CABAC instructions and the accelerator prototyped in a state-of-the-art FPGA technology.
ISSN:0098-3063
1558-4127
DOI:10.1109/TCE.2006.1649684