Very small FPGA application-specific instruction processor for AES

This paper presents two low-area designs for the advanced encryption standard on field-programmable gate arrays (FPGAs). Both these designs are believed to be the smallest to date. The first design is an 8-bit application-specific instruction processor, which supports key expansion (currently progra...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2006-07, Vol.53 (7), p.1477-1486
Main Authors: Good, T., Benaissa, M.
Format: Article
Language:English
Subjects:
8 bit
advanced encryption standard (AES)
Aging
Application specific integrated circuits
Application specific processors
application-specific instruction processor (ASIP)
Circuits
Clocks
Cryptography
Design engineering
Encryption
Field programmable gate arrays
field-programmable gate array (FPGA)
Gate arrays
Government
Hardware
low area
Microcontrollers
Microprocessors
Priorities
Throughput
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Summary:This paper presents two low-area designs for the advanced encryption standard on field-programmable gate arrays (FPGAs). Both these designs are believed to be the smallest to date. The first design is an 8-bit application-specific instruction processor, which supports key expansion (currently programmed for a 128-bit key), encipher and decipher. The design utilizes less than 60% of the resources of the smallest available Xilinx Spartan II FPGA (XC2S15). The average encipher-decipher throughput is 2.1 Mbps when clocked at 70 MHz. The design has numerous applications where low area and low power are priorities. The second design, using the Xilinx PicoBlaze soft core is included to provide an embedded 8-bit microcontroller comparison baseline.
ISSN:1549-8328
1057-7122
1558-0806
DOI:10.1109/TCSI.2006.875179