Background interstage gain calibration technique for pipelined ADCs

• Published in: IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2005-01, Vol.52 (1), p.32-43
• Main Authors: Keane, J.P., Hurst, P.J., Lewis, S.H.
• Format: Article
• Language: English
• Subjects: Analog-digital conversion; Calibration; Convergence; Error correction; Gain measurement; Linearity; linearization techniques; nonlinear circuits; Pipelines; Redundancy; Statistics; Voltage
• ISSN: 1549-8328; 1057-7122; 1558-0806
• DOI: 10.1109/TCSI.2004.839534

A background self-calibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic analog-to-digital converters (ADCs). Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital post-processing. The proposed technique allows faster convergence and has less dependence on input signal statistics than a similar technique described by Murmann and Boser. Simulation results are presented for a 12-bit pipelined ADC architecture, similar to that described by Murmann and Boser, using nonideal interstage residue amplifiers. With calibration, the simulations show a signal-to-noise-and-distortion-ratio performance of 72 dB and a spurious-free dynamic range performance of 112 dB, with calibration tracking time constants of approximately 8/spl times/10/sup 5/ sample periods, which is over ten times faster than that reported by Murmann and Boser at a similar performance level.