A family of compact genetic algorithms for intrinsic evolvable hardware

For many evolvable hardware applications, small size and power efficiency are critical design considerations. One manner in which significant memory, and thus, power and space savings can be realized in a hardware-based evolutionary algorithm is to represent populations of candidate solutions as pro...

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Bibliographic Details
Published in:IEEE transactions on evolutionary computation 2004-04, Vol.8 (2), p.111-126
Main Authors: Gallagher, J.C., Vigraham, S., Kramer, G.
Format: Article
Language:English
Subjects:
Applied sciences
Artificial intelligence
Automatic control
Bioinformatics
Computational modeling
Computer science
control theory
systems
Evolutionary computation
Exact sciences and technology
Field programmable gate arrays
Genetic algorithms
Genomics
Hardware
Learning and adaptive systems
Random access memory
Studies
Very large scale integration
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Summary:For many evolvable hardware applications, small size and power efficiency are critical design considerations. One manner in which significant memory, and thus, power and space savings can be realized in a hardware-based evolutionary algorithm is to represent populations of candidate solutions as probability vectors rather than as sets of bit strings. The compact genetic algorithm (CGA) is a probability vector-based evolutionary algorithm that can be efficiently and elegantly implemented in digital hardware. Unfortunately, the CGA is a very weak, first order, evolutionary algorithm that is unlikely to possess sufficient search power to enable intrinsic evolvable hardware applications. In this paper, we further develop a number of modifications to the basic CGA that significantly improve its search efficacy without substantially increasing the size and complexity of its hardware implementation. The paper provides both benchmark results demonstrating increased efficacy and a conceptual data path/microcontroller design suitable for implementation in digital hardware. Following, it demonstrates efficient implementation by making a head-to-head comparison of field programmable gate array implementations of both the classic CGA and a member of our family of modifications. The paper concludes with a discussion of future research, including several additional extensions that we expect will further increase search efficacy without increasing implementation cost.
ISSN:1089-778X
1941-0026
DOI:10.1109/TEVC.2003.820662