An experimental study of scalability in shield-based on-wafer CMOS test fixtures

In this paper, the possibilities of employing full scalability to on-wafer complementary metal-oxide-semiconductor (CMOS) test fixtures is studied experimentally. Several test fixtures and in-fixture sets were fabricated and measured in order to find the significant parasitic components in shield-ba...

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Bibliographic Details
Published in:IEEE transactions on microwave theory and techniques 2004-03, Vol.52 (3), p.945-953
Main Authors: Kaija, T., Ristolainen, E.O.
Format: Article
Language:English
Subjects:
Calibration
CMOS technology
Electrical resistance measurement
Fixtures
Inductance
Integrated circuit technology
Parasitic capacitance
Probes
Scalability
Testing
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Summary:In this paper, the possibilities of employing full scalability to on-wafer complementary metal-oxide-semiconductor (CMOS) test fixtures is studied experimentally. Several test fixtures and in-fixture sets were fabricated and measured in order to find the significant parasitic components in shield-based fixtures. An improved method for applying bi-directional scaling to on-wafer shield-based test fixtures is proposed. This method takes into account the parasitic series resistance, series inductance, and parallel capacitance that are present in the test fixture. The proposed method can be used successfully in commonly known deembedding methods. This is verified through measurements. The test fixtures were fabricated on top of a lossy substrate using double-poly, three-metal-layer 0.35-/spl mu/m CMOS technology.
ISSN:0018-9480
1557-9670
DOI:10.1109/TMTT.2004.823576