Optimal path routing in single- and multiple-clock domain systems

Shrinking process geometries and the increasing use of intellectual property components in system-on-chip designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-chip routing will require multiple clock cycles. Another is the integration of independently...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2003-11, Vol.22 (11), p.1580-1588
Main Authors: Hassoun, S., Alpert, C.J.
Format: Article
Language:English
Subjects:
Algorithms
Buffers
Clocks
Construction
Delay
Design engineering
Dynamical systems
Frequency synchronization
Geometry
Insertion
Integrated circuit interconnections
Intellectual property
Optimization
Pipeline processing
Registers
Routing
Synchronous
System-on-a-chip
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Summary:Shrinking process geometries and the increasing use of intellectual property components in system-on-chip designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-chip routing will require multiple clock cycles. Another is the integration of independently clocked components. This paper explores simultaneous routing and buffer insertion in the context of single- and multiple-clock domains. We present two optimal and efficient polynomial algorithms that build upon the dynamic programming fast path framework. The first algorithm solves the problem of finding the minimum latency path for a single-clock domain system. The second considers routing between two components that are locally synchronous yet globally asynchronous to each other. Both algorithms can be used for interconnect planning. Experimental results verify the correctness and practicality of our approach.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2003.818378