A compact analytical model for asymmetric single-electron tunneling transistors

Analytical model for asymmetric single-electron tunneling transistors (SETTs), in which resistance and capacitance parameters of source/drain junctions are not equal, has been developed. The model is based on the steady-state master equation, takes only the two most-probable charging states into acc...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2003-02, Vol.50 (2), p.455-461
Main Authors: Inokawa, H., Takahashi, Y.
Format: Article
Language:English
Subjects:
Asymmetry
Capacitance
Coulomb friction
Drains
Electric potential
Mathematical analysis
Mathematical models
Semiconductor device modeling
Semiconductor devices
Voltage
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Summary:Analytical model for asymmetric single-electron tunneling transistors (SETTs), in which resistance and capacitance parameters of source/drain junctions are not equal, has been developed. The model is based on the steady-state master equation, takes only the two most-probable charging states into account, and is therefore very simple. Even so, it can accurately reproduce the peculiar behaviors of an asymmetric SETT, such as the skew in the drain current-gate voltage characteristics and the Coulomb staircase in the drain current-drain voltage characteristic. Analytical expressions for the charge in the Coulomb island and the capacitance components of the SETT are also derived according to the same scheme, and it is demonstrated that the model can precisely describe the various aspects of the SETT behavior.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2002.808554