Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures

This paper proposes a single-ISA heterogeneousmulti-core architecture as a mechanism to reduce processorpower dissipation. It assumes a single chip containing a diverseset of cores that target different performance levels and consumedifferent levels of power. During an application's execution,s...

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Bibliographic Details
Published in:IEEE computer architecture letters 2003-01, Vol.2 (1), p.2-2
Main Authors: Kumar, R., Farkas, K., Jouppi, N.P., Ranganathan, P., Tullsen, D.M.
Format: Article
Language:English
Subjects:
Application software
chip multiprocessor
Chips
Computer architecture
Computer programs
Computer science
Consumption
Cost engineering
Costs
Dissipation
Energy consumption
Fans
low-power architecture
Microprocessors
Packaging
Power dissipation
Power engineering and energy
Reduction
Software
System software
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Summary:This paper proposes a single-ISA heterogeneousmulti-core architecture as a mechanism to reduce processorpower dissipation. It assumes a single chip containing a diverseset of cores that target different performance levels and consumedifferent levels of power. During an application's execution,system software dynamically chooses the most appropriate core tomeet specific performance and power requirements. It describesan example architecture with five cores of varying performanceand complexity. Initial results demonstrate a five-fold reductionin energy at a cost of only 25% performance.
ISSN:1556-6056
1556-6064
DOI:10.1109/L-CA.2003.6