Speed superiority of scaled double-gate CMOS

Unloaded ring-oscillator simulations, performed with a generic process/physics-based compact model for double-gate (DG) MOSFETs and supplemented with model-predicted on-state currents and gate capacitances for varying supply voltages (V/sub DD/), are used to show and explain the speed superiority of...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2002-05, Vol.49 (5), p.808-811
Main Authors: Fossum, J.G., Lixin Ge, Meng-Hsueh Chiang
Format: Article
Language:English
Subjects:
Circuits
CMOS
CMOS integrated circuits
Computer simulation
Devices
Electric potential
Gates
MOSFETs
Voltage
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Summary:Unloaded ring-oscillator simulations, performed with a generic process/physics-based compact model for double-gate (DG) MOSFETs and supplemented with model-predicted on-state currents and gate capacitances for varying supply voltages (V/sub DD/), are used to show and explain the speed superiority of extremely scaled DG CMOS over the single-gate (e.g., bulk-Si) counterpart. The DG superiority for unloaded circuits is most substantive for low V/sub DD/ < /spl sim/1 V.
ISSN:0018-9383
1557-9646
DOI:10.1109/16.998588