An on-chip clock-adjusting circuit with sub-100-ps resolution for a high-speed DRAM interface

A novel fully digital fine-delay circuit for a high-speed DRAM interface is proposed. The circuit consists of arrayed delay components and generates a group of rail-to-rail delayed signals with sub-100-ps resolution. The input-coupling element (squeezer) in the delay component converges the variatio...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2000-08, Vol.47 (8), p.771-775
Main Authors: Noda, H., Aoki, M., Tanaka, H., Nagashima, O., Aoki, H.
Format: Article
Language:English
Subjects:
Circuit testing
Clocks
Delay
Feedback circuits
Feedback loop
Frequency
Phase locked loops
Random access memory
Sampling methods
Signal resolution
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Summary:A novel fully digital fine-delay circuit for a high-speed DRAM interface is proposed. The circuit consists of arrayed delay components and generates a group of rail-to-rail delayed signals with sub-100-ps resolution. The input-coupling element (squeezer) in the delay component converges the variations of the resolution. A test device design using 0.35-/spl mu/m technology demonstrates that a resolution of 26 ps can be achieved. A clock-recovery circuit using this circuit has a two-clock-cycle lock time and sub-100-ps error.
ISSN:1057-7130
1558-125X
DOI:10.1109/82.861409