Timing optimization on routed designs with incremental placement and routing characterization

Wire delay estimation has been a problem in designs of very deep submicron (VDSM) technologies with feature size under 0.25 /spl mu/m. The conventional back-annotation approach does not guarantee timing convergence due to different estimation techniques for prelayout and post-layout timing. In this...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2000-02, Vol.19 (2), p.188-196
Main Authors: Changfan, Chieh, Hsu, Yu-Chin, Tsai, Fur-Shing
Format: Article
Language:English
Subjects:
Algorithms
Computer aided design
Convergence
Delay
Delay estimation
Design engineering
Design optimization
Logic
Optimization
Optimization methods
Parasitic capacitance
Routing
Time measurements
Timing
Very large scale integration
Wire
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Summary:Wire delay estimation has been a problem in designs of very deep submicron (VDSM) technologies with feature size under 0.25 /spl mu/m. The conventional back-annotation approach does not guarantee timing convergence due to different estimation techniques for prelayout and post-layout timing. In this paper, a post-routing timing optimization algorithm is presented. Experimental results show that this algorithm provides better result after detail routing is completed.
ISSN:0278-0070
1937-4151
DOI:10.1109/43.828547