Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2011-09, Vol.58 (9), p.2051-2060
• Main Authors: Waheed, K., Staszewski, R. B., Dulger, F., Ullah, M. S., Vamvakos, S. D.
• Format: Article
• Language: English
• Subjects: All-digital PLL; Clocks; deadband; Delay; Digital; digital-to-time converter (DTC); Dithering; Dithers; Feedback; Frequency modulation; Inverters; limit cycles; Nanostructure; Noise; Oscillators; phase error; Phase locked loops; Phase-locked loop; Quantization; Sampling; short dither sequence; time-to-digital converter (TDC)
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2011.2163981

We propose an enhancement to the digital phase detection mechanism in an all-digital phase-locked loop (ADPLL) by randomization of the frequency reference using carefully chosen dither sequences. This dithering renders the digital phase detector, realized as a time-to-digital converter (TDC), free from any phase domain spurious tones generated as a consequence of an ill-conditioned sampling of the feedback variable oscillator phase. In modern nanoscale technologies, TDC has a time quantization of 5 to 30 ps. This deadband can potentially result in spurious tones, whenever a near integer-N relationship arises between the oscillator frequency and the TDC sampling process. This work proposes injection of a spectrum-friendly short sequence dither into the reference clock signal to overcome the quantization introduced limit-cycles. This results in robust phase tracking performance and spurious-free operation of the ADPLL, which was verified in a 65-nm CMOS GSM/EDGE transmitter.