Feasibility of 0.18 [mu]m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

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Bibliographic Details
Published in:IEEE transactions on electron devices 2001-09, Vol.48 (9), p.2065
Main Authors: Maeda, S, Wada, Y, Yamamoto, K, Komurasaki, H, Matsumoto, T, Hirano, Y, Iwamatsu, T, Yamaguchi, Y, Ipposhi, T, Ueda, K, Mashiko, K, Maegawa, S, Inuishi, M
Format: Article
Language:English
Online Access:Get full text
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ISSN:0018-9383
1557-9646
DOI:10.1109/16.944197