CNoC: High-Radix Clos Network-on-Chip

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2011-12, Vol.30 (12), p.1897-1910
• Main Authors: Yu-Hsiang Kao, Ming Yang, Artan, N. S., Chao, H. J.
• Format: Article
• Language: English
• Subjects: Algorithms; Chip multiprocessor; clos network; Delay; Design engineering; Heuristic algorithms; High speed; high-radix NoC; Network topology; Network-on-a-chip; network-on-chip; Power demand; Routers; Scheduling algorithm; Studies; Throughput; Topology; Traffic engineering; Traffic flow
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2011.2164538

Many high-radix network-on-chip (NoC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe high-radix Clos network-on-chip (CNoC) is the most promising with its low average hop counts and good load-balancing characteristics. In this paper, we propose: 1) a high-radix router architecture with virtual output queue (VOQ) buffer structure and packet mode dual round-robin matching (PDRRM) scheduling algorithm to achieve high speed and high throughput in CNoC; 2) the design of hierarchical round-robin arbiter for high-radix high-speed NoC routers; and 3) a heuristic floor-planning algorithm to minimize the power consumption caused by the long wires. Experimental results show that the throughput of a 64-node three-stage CNoC under uniform traffic increases from 62% to 78% by replacing the baseline virtual channel routers with PDRRM VOQ routers. We also compared the delay, power, and area performance of the 64-node CNoC with other NoC topologies under various synthetic traffic patterns and SPLASH-2 benchmark traces. The simulation results show that in general CNoC improves the throughput, low-load delay, and energy efficiency over the compared NoC topologies.