Low standby power state storage for sub-130-nm technologies

Handheld and other battery-powered ICs require process scaling to increase functional integration and reduce active power consumption. Scaling also increases leakage current components to the point where standby power is frequently a limiting design factor. A scheme combining low-leakage thick-gate...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 2005-02, Vol.40 (2), p.498-506
Main Authors: Clark, L.T., Ricci, F., Biyani, M.
Format: Article
Language:English
Subjects:
Applied sciences
Batteries
Circuit design
Circuit properties
Circuit synthesis
Circuits
Constraining
Digital circuits
Dynamic voltage scaling
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Energy consumption
Exact sciences and technology
Frequency
Functional integration
Latches
Leakage current
Leakage currents
logic circuits
low power
Power consumption
Power supplies
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
sequential logic circuits
Shadows
Threshold voltage
Transistors
Tunneling
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Handheld and other battery-powered ICs require process scaling to increase functional integration and reduce active power consumption. Scaling also increases leakage current components to the point where standby power is frequently a limiting design factor. A scheme combining low-leakage thick-gate shadow latches and high-performance transistors is presented that decouples performance from standby power in sub-130-nm technologies. Circuit design and operation, including pulse-clocked latches, use of dynamic circuits, and inclusion of scan is presented. The approach is validated by experimental results on a 90-nm process.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2004.840987