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Low standby power state storage for sub-130-nm technologies
Handheld and other battery-powered ICs require process scaling to increase functional integration and reduce active power consumption. Scaling also increases leakage current components to the point where standby power is frequently a limiting design factor. A scheme combining low-leakage thick-gate...
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| Published in: | IEEE journal of solid-state circuits 2005-02, Vol.40 (2), p.498-506 |
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| Main Authors: | , , |
| Format: | Article |
| Language: | English |
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| cited_by | cdi_FETCH-LOGICAL-c383t-9cdd2dce8c91a3dfd78433c8a9a6b4f5f20cbff345287c7c0b321048ba7ba5763 |
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| cites | cdi_FETCH-LOGICAL-c383t-9cdd2dce8c91a3dfd78433c8a9a6b4f5f20cbff345287c7c0b321048ba7ba5763 |
| container_end_page | 506 |
| container_issue | 2 |
| container_start_page | 498 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 40 |
| creator | Clark, L.T. Ricci, F. Biyani, M. |
| description | Handheld and other battery-powered ICs require process scaling to increase functional integration and reduce active power consumption. Scaling also increases leakage current components to the point where standby power is frequently a limiting design factor. A scheme combining low-leakage thick-gate shadow latches and high-performance transistors is presented that decouples performance from standby power in sub-130-nm technologies. Circuit design and operation, including pulse-clocked latches, use of dynamic circuits, and inclusion of scan is presented. The approach is validated by experimental results on a 90-nm process. |
| doi_str_mv | 10.1109/JSSC.2004.840987 |
| format | article |
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Scaling also increases leakage current components to the point where standby power is frequently a limiting design factor. A scheme combining low-leakage thick-gate shadow latches and high-performance transistors is presented that decouples performance from standby power in sub-130-nm technologies. Circuit design and operation, including pulse-clocked latches, use of dynamic circuits, and inclusion of scan is presented. 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The approach is validated by experimental results on a 90-nm process.</description><subject>Applied sciences</subject><subject>Batteries</subject><subject>Circuit design</subject><subject>Circuit properties</subject><subject>Circuit synthesis</subject><subject>Circuits</subject><subject>Constraining</subject><subject>Digital circuits</subject><subject>Dynamic voltage scaling</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Energy consumption</subject><subject>Exact sciences and technology</subject><subject>Frequency</subject><subject>Functional integration</subject><subject>Latches</subject><subject>Leakage current</subject><subject>Leakage currents</subject><subject>logic circuits</subject><subject>low power</subject><subject>Power consumption</subject><subject>Power supplies</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Scaling also increases leakage current components to the point where standby power is frequently a limiting design factor. A scheme combining low-leakage thick-gate shadow latches and high-performance transistors is presented that decouples performance from standby power in sub-130-nm technologies. Circuit design and operation, including pulse-clocked latches, use of dynamic circuits, and inclusion of scan is presented. The approach is validated by experimental results on a 90-nm process.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2004.840987</doi><tpages>9</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2005-02, Vol.40 (2), p.498-506 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_proquest_journals_911980439 |
| source | IEEE Electronic Library (IEL) Journals |
| subjects | Applied sciences Batteries Circuit design Circuit properties Circuit synthesis Circuits Constraining Digital circuits Dynamic voltage scaling Electric, optical and optoelectronic circuits Electronic circuits Electronics Energy consumption Exact sciences and technology Frequency Functional integration Latches Leakage current Leakage currents logic circuits low power Power consumption Power supplies Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices sequential logic circuits Shadows Threshold voltage Transistors Tunneling |
| title | Low standby power state storage for sub-130-nm technologies |
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