Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking

This paper describes the core and I/O clocking architecture of the next generation Intel reg Coretrade micro-architecture processor (Nehalem), designed on a 45 nm process technology. Local PLL placement provides modularity and power-efficient scalability by allowing independent frequency and voltage...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2009-04, Vol.44 (4), p.1121-1129
Main Authors: Kurd, N., Mosalikanti, P., Neidengard, M., Douglas, J., Kumar, R.
Format: Article
Language:English
Subjects:
Bandwidth
Clocks
delay-locked loop (DLL)
Drives
Frequency
Intel¯ QuickPath
interconnect
Jitter
Linearity
memory controller
Phase locked loops
phase-locked loop (PLL)
Process design
Scalability
Voltage
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Summary:This paper describes the core and I/O clocking architecture of the next generation Intel reg Coretrade micro-architecture processor (Nehalem), designed on a 45 nm process technology. Local PLL placement provides modularity and power-efficient scalability by allowing independent frequency and voltage domains. Fast-locking, low-skew PLLs are used to achieve 56% lock time reduction and 30% long-tem jitter improvement. Adaptive frequency, supply, and duty cycle mechanisms combine for up to 5% core frequency gain at iso-voltage. Jitter attenuating DLLs with enhanced linearity and plusmn15% duty cycle correction drive a differential, low-swing I/O receiver clock distribution, reducing jitter by 25% and enabling 25.6 GB/s Intel reg QuickPath Interconnect bandwidth and three-channel DDR3 traffic up to 32 GB/s.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2009.2014023