Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

• Published in: IEEE journal of solid-state circuits 2009-04, Vol.44 (4), p.1227-1234
• Main Author: Takeuchi, K.
• Format: Article
• Language: English
• Subjects: Applied sciences; Capacitance; Circuits; Co-design; Computer systems; Computers, microcomputers; Contacts; Costs; Design. Technologies. Operation analysis. Testing; Drives; Electronics; Exact sciences and technology; Flash memory; Flash memory (computers); Hardware; High speed; Integrated circuits; Integrated circuits by function (including memories and processors); Interleaved codes; Microcomputers; NAND controller; NAND flash memory; Noise; Personal computers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Servers; Size control; Solid state circuits; solid state drive; SSD; Weight control
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2009.2014027

As the cell size of the NAND flash memory has been scaled down by 40%-50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller circuits is essential. In this paper, three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line program, and the intelligent interleaving, are proposed. In the selective bit-line precharge scheme, an unnecessary bit-line precharge is removed during the verify-read and consequently the current consumption decreases by 23%. In the advanced source-line program scheme, a hierarchical source-line structure is adopted. The load capacitance during the program pulse is reduced by 90% without a die size overhead. As a result, the current consumption is reduced by 48%. Finally, with the intelligent interleaving, a current peak is suppressed and a high-speed parallel write operation of the NAND flash memories is achieved. By using these three technologies, both the NAND flash memory and the NAND controller circuits are best optimized. At the sub-30 nm generation, the current consumption of the NAND flash memory decreases by 60% and the SSD speed improves by 150% without a cost penalty or circuit noise.