A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

• Published in: IEEE journal of solid-state circuits 2005-11, Vol.40 (11), p.2148-2158
• Main Authors: Hyung-Rok Lee, Moon-Sang Hwang, Bong-Joon Lee, Young-Deok Kim, Dohwan Oh, Jaeha Kim, Sang-Hyun Lee, Deog-Kyoon Jeong, Kim, W.
• Format: Article
• Language: English
• Subjects: 10 Gb/s; Applied sciences; Channels; Chips; Circuit optimization; Circuit properties; Circuits; Circuits of signal characteristics conditioning (including delay circuits); Clocks; CMOS process; Design. Technologies. Operation analysis. Testing; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Ethernet; Ethernet networks; Exact sciences and technology; Frequency dividers; Integrated circuits; Oscillators, resonators, synthetizers; phase-locked loop; Robustness; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Temperature control; Transceivers; Tuning; Voltage; Voltage control; voltage-controlled oscillator (VCO); Voltage-controlled oscillators; XAUI
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2005.857360

This paper describes the design and the implementation of a fully integrated 10 Gb Ethernet transceiver in a 0.13-/spl mu/m CMOS process using only a 1.2 V supply. A coarse control algorithm that combines a voltage range monitoring circuit with a frequency lock detector provides a robust operation against process, voltage, and temperature (PVT) variations for a VCO with a ring oscillator. With the use of a blind oversampling DPLL architecture, four channels of XAUI transceivers can share a single PLL, eliminating the clock synchronization problem between channels. Also, the total number of clock domains for the entire chip is reduced to three, making the integration of the XAUI with the 10G transceiver much simpler. The test chip consumes 898 mW from a 1.2 V supply.