Design and Analysis of System on a Chip Encoder for JPEG2000

Much work has been performed on optimizing the throughput of the block coding system within JPEG2000. However, the question remains as to whether providing parallel simple block coders provides a cheaper method of increasing throughput than complicated optimized block coders. We present the analysis...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology 2009-02, Vol.19 (2), p.215-225
Main Authors: Dyer, M., Nooshabadi, S., Taubman, D.
Format: Article
Language:English
Subjects:
Applied sciences
Arithmetic coder
block coder
Block codes
Blocking
Circuit properties
Code standards
Coders
Coding
Coding, codes
Computer programs
Design engineering
Design optimization
digital architectures
Discrete wavelet transforms
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
embedded block coder with optimal truncation (EBCOT)
Encoders
Exact sciences and technology
Hardware
Image processing
Information, signal and communications theory
Integrated circuits
Integrated circuits by function (including memories and processors)
JPEG2000
MQ coder
Optimization
Optimization methods
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal and communications theory
Signal convertors
Signal processing
Software standards
software/hardware codesign
System-on-a-chip
Telecommunications and information theory
Throughput
Transform coding
Wavelet transforms
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Description
Summary:Much work has been performed on optimizing the throughput of the block coding system within JPEG2000. However, the question remains as to whether providing parallel simple block coders provides a cheaper method of increasing throughput than complicated optimized block coders. We present the analysis and results for a system on a chip (SoC) software/hardware codesign platform, for parallel coding in JPEG2000 compression standard. We design both a simple and a high performance, optimized peripheral encoder as a hardware accelerator for the JPEG2000 SoC encoding system. The system is implemented on an Altera NIOS II processor with flexible integrated peripheral. We show that there are optimum numbers of parallel block coders and scheduling granularity per row of codeblocks, and that parallel optimized encoders outperform parallel simple encoders. We also demonstrate that the block coding system becomes work starved rather than memory blocked when many parallel coders are present, indicating a discrete wavelet transform bottleneck.
ISSN:1051-8215
1558-2205
DOI:10.1109/TCSVT.2008.2009245