A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment tem...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2006-04, Vol.41 (4), p.883-890
Main Authors: Iizuka, K., Matsui, H., Ueda, M., Daito, M.
Format: Article
Language:English
Subjects:
Adaptive control
Adaptive system
Amplifiers
Analog circuits
Analog-digital conversion
analog-to-digital (A/D) converters
analog-to-digital conversion (ADC)
Applied sciences
Bias
calibration
Chip formation
Chip scale packaging
Circuit properties
CMOS analog integrated circuits
CMOS integrated circuits
CMOS technology
Consumption
Electric potential
Electric, optical and optoelectronic circuits
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Nonlinearity
Optimization
pipeline processing
Power amplifiers
Programmable control
Sampling
Sampling methods
Signal convertors
Temperature control
Temperature dependence
Voltage control
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Summary:This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment temperature, and power-supply voltage, as well as the variations in chip fabrication. It utilizes information from the digital calibration process and does not require additional analog circuits. The prototype ADC occupies an area of 0.5/spl times/2.3 mm/sup 2/ in a 0.18-/spl mu/m dual-gate CMOS technology; with a power supply of 2.8 V, it consumes 19.2, 33.7, 50.5, and 72.8 mW when operating at 10, 20, 30, and 40 MS/s, respectively. The peak differential nonlinearity (DNL) is less than 0.5 least significant bit (LSB) for all the sampling speeds with temperature variation up to 80/spl deg/C. When operated at 20 MS/s with 1-MHz input, the ADC achieves 72.1-dB SNR and 71.1-dB SNDR.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2006.870788