The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

• Published in: IEEE journal of solid-state circuits 2006-08, Vol.41 (8), p.1830-1845
• Main Authors: Dickson, T.O., Yau, K.H.K., Chalvatzis, T., Mangan, A.M., Laskin, E., Beerkens, R., Westergaard, P., Tazlauanu, M., Ming-Ta Yang, Voinigescu, S.P.
• Format: Article
• Language: English
• Subjects: Algorithm design and analysis; Amplifiers; Applied sciences; BiCMOS integrated circuits; Characteristic current densities; Circuit properties; Circuits; CMOS; CMOS logic circuits; CMOS process; Current density; Design methodology; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Germanium silicon alloys; High speed; Integrated circuits; Logic; low-noise transimpedance amplifiers; Molecular electronics, nanoelectronics; MOS-CML; MOSFETs; nanoscale CMOS; Nanostructure; Noise; Noise figure; operational amplifiers; output drivers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SiGe BiCMOS; Silicon germanides; Silicon germanium; SOI; Transistors; wave-shape control
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2006.875301

This paper provides evidence that, as a result of constant-field scaling, the peak f T (approx. 0.3 mA/mum), peak f MAX (approx. 0.2 mA/mum), and optimum noise figure NF MIN (approx. 0.15 mA/mum) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers