A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller

A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-mum standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2 mum 2 three-transistor (3T) OTP cells where each cell util...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2006-09, Vol.41 (9), p.2115-2124
Main Authors: Hyouk-Kyu Cha, Ilhyun Yun, Jinbong Kim, Byeong-Cheol So, Kanghyup Chun, Nam, I., Kwyro Lee
Format: Article
Language:English
Subjects:
Antifuses
Applied sciences
Circuits
CMOS
CMOS antifuse
CMOS OTP
CMOS process
CMOS technology
Design. Technologies. Operation analysis. Testing
Electric breakdown
Electronics
embedded PROM
EPROM
Exact sciences and technology
gate-oxide breakdown
Integrated circuits
Integrated circuits by function (including memories and processors)
microcontroller
Microcontrollers
Nonvolatile memory
OTP ROM
PROM
Random access memory
Read only memory
Semiconductor devices
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
Static random access memory
Transistors
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Summary:A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-mum standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2 mum 2 three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external I 2 C master device such as universal I 2 C serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9 mm 2 . This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2006.880603