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A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller
A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-mum standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2 mum 2 three-transistor (3T) OTP cells where each cell util...
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Published in: | IEEE journal of solid-state circuits 2006-09, Vol.41 (9), p.2115-2124 |
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container_issue | 9 |
container_start_page | 2115 |
container_title | IEEE journal of solid-state circuits |
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creator | Hyouk-Kyu Cha Ilhyun Yun Jinbong Kim Byeong-Cheol So Kanghyup Chun Nam, I. Kwyro Lee |
description | A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-mum standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2 mum 2 three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external I 2 C master device such as universal I 2 C serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9 mm 2 . This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications |
doi_str_mv | 10.1109/JSSC.2006.880603 |
format | article |
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The proposed 32-KB OTP ROM cell array consists of 4.2 mum 2 three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external I 2 C master device such as universal I 2 C serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9 mm 2 . This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2006.880603</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Antifuses ; Applied sciences ; Circuits ; CMOS ; CMOS antifuse ; CMOS OTP ; CMOS process ; CMOS technology ; Design. Technologies. Operation analysis. Testing ; Electric breakdown ; Electronics ; embedded PROM ; EPROM ; Exact sciences and technology ; gate-oxide breakdown ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; microcontroller ; Microcontrollers ; Nonvolatile memory ; OTP ROM ; PROM ; Random access memory ; Read only memory ; Semiconductor devices ; Semiconductor electronics. Microelectronics. Optoelectronics. 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(IEEE) 2006</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c352t-24709bfeabc8d47d655044471b48abf8d0f78f4da36321a57e2b1c28f790b06a3</citedby><cites>FETCH-LOGICAL-c352t-24709bfeabc8d47d655044471b48abf8d0f78f4da36321a57e2b1c28f790b06a3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1683903$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27915,27916,54787</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=18075830$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Hyouk-Kyu Cha</creatorcontrib><creatorcontrib>Ilhyun Yun</creatorcontrib><creatorcontrib>Jinbong Kim</creatorcontrib><creatorcontrib>Byeong-Cheol So</creatorcontrib><creatorcontrib>Kanghyup Chun</creatorcontrib><creatorcontrib>Nam, I.</creatorcontrib><creatorcontrib>Kwyro Lee</creatorcontrib><title>A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-mum standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2 mum 2 three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external I 2 C master device such as universal I 2 C serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9 mm 2 . This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications</description><subject>Antifuses</subject><subject>Applied sciences</subject><subject>Circuits</subject><subject>CMOS</subject><subject>CMOS antifuse</subject><subject>CMOS OTP</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electric breakdown</subject><subject>Electronics</subject><subject>embedded PROM</subject><subject>EPROM</subject><subject>Exact sciences and technology</subject><subject>gate-oxide breakdown</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>microcontroller</subject><subject>Microcontrollers</subject><subject>Nonvolatile memory</subject><subject>OTP ROM</subject><subject>PROM</subject><subject>Random access memory</subject><subject>Read only memory</subject><subject>Semiconductor devices</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Operation analysis. Testing</topic><topic>Electric breakdown</topic><topic>Electronics</topic><topic>embedded PROM</topic><topic>EPROM</topic><topic>Exact sciences and technology</topic><topic>gate-oxide breakdown</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>microcontroller</topic><topic>Microcontrollers</topic><topic>Nonvolatile memory</topic><topic>OTP ROM</topic><topic>PROM</topic><topic>Random access memory</topic><topic>Read only memory</topic><topic>Semiconductor devices</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Semiconductors</topic><topic>Static random access memory</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Hyouk-Kyu Cha</creatorcontrib><creatorcontrib>Ilhyun Yun</creatorcontrib><creatorcontrib>Jinbong Kim</creatorcontrib><creatorcontrib>Byeong-Cheol So</creatorcontrib><creatorcontrib>Kanghyup Chun</creatorcontrib><creatorcontrib>Nam, I.</creatorcontrib><creatorcontrib>Kwyro Lee</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Hyouk-Kyu Cha</au><au>Ilhyun Yun</au><au>Jinbong Kim</au><au>Byeong-Cheol So</au><au>Kanghyup Chun</au><au>Nam, I.</au><au>Kwyro Lee</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2006-09-01</date><risdate>2006</risdate><volume>41</volume><issue>9</issue><spage>2115</spage><epage>2124</epage><pages>2115-2124</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-mum standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2 mum 2 three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external I 2 C master device such as universal I 2 C serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9 mm 2 . This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2006.880603</doi><tpages>10</tpages></addata></record> |
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subjects | Antifuses Applied sciences Circuits CMOS CMOS antifuse CMOS OTP CMOS process CMOS technology Design. Technologies. Operation analysis. Testing Electric breakdown Electronics embedded PROM EPROM Exact sciences and technology gate-oxide breakdown Integrated circuits Integrated circuits by function (including memories and processors) microcontroller Microcontrollers Nonvolatile memory OTP ROM PROM Random access memory Read only memory Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Semiconductors Static random access memory Transistors |
title | A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller |
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