Hardness-by-design approach for 0.15 [micro]m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2005-12, Vol.52 (6), p.2524
Main Authors: Makihara, A, Midorikawa, M, Yamaguchi, T, Iide, Y, Yokose, T, Tsuchiya, Y, Arimitsu, T, Asai, H, Shindou, H, Kuboyama, S, Matsuda, S
Format: Article
Language:English
Online Access:Get full text
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ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2005.860716