Joint Prediction Algorithm and Architecture for Stereo Video Hybrid Coding Systems

• Published in: IEEE transactions on circuits and systems for video technology 2006-11, Vol.16 (11), p.1324-1337
• Main Authors: DING, Li-Fu, CHIEN, Shao-Yi, CHEN, Liang-Gee
• Format: Article
• Language: English
• Subjects: 3-D video; Algorithms; Applied sciences; Architecture; Bandwidth; Blocking; Coding; Complexity; Computation; Computational complexity; Computer architecture; Design. Technologies. Operation analysis. Testing; Detection, estimation, filtering, equalization, prediction; Electronics; Exact sciences and technology; Hardware; Hardware architecture; Image processing; Information, signal and communications theory; Integrated circuits; Integrated circuits by function (including memories and processors); joint prediction algorithm (JPA); MPEG 4 Standard; Prediction algorithms; Random access memory; Rate-distortion; Scalability; Searching; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal and communications theory; Signal processing; Signal, noise; stereo video coding; Studies; Telecommunications and information theory; Video coding
• ISSN: 1051-8215; 1558-2205
• DOI: 10.1109/TCSVT.2006.883510

3-D video will be the most prominent video technology in the next generation. Among the 3-D video technologies, stereo video systems are considered to be realized first in the near future. Stereo video systems require double bandwidth and more than twice the computational complexity relative to mono-video systems. Thus, an efficient coding scheme is necessary for transmitting stereo video. In this paper, a new structure of prediction core in stereo video coding systems is proposed from the algorithm level to the hardware architecture level. The joint prediction algorithm (JPA), which combines three prediction schemes, is proposed for high coding efficiency and low computational complexity. It makes the system outperform MPEG-4 temporal scalability and simple profile by 2-3 dB in rate-distortion performance. Besides, JPA also utilizes the characteristics of stereo video and successfully reduces about 80% computational complexity. Then, a new hardware architecture of the prediction core based on JPA and a modified hierarchical search block-matching algorithm is proposed. With a special data flow, no bubble cycles exist during the block-matching process. The proposed architecture also adopts the near-overlapped candidates reuse scheme to save the heavy burden of data access. Besides, both on-chip memory requirement and off-chip memory bandwidth can be reduced by the proposed new scheduling. Compared with the hardware requirement for the implementation of full search block-matching algorithm, only 11.5% on-chip SRAM and 3.3% processing elements are needed with a tiny PSNR drop, making it area-efficient while maintaining high stereo video quality and processing capability