Two Complementary Approaches for Studying the Effects of SEUs on Digital Processors

This paper describes two different but complementary approaches that can be used to perform SEU-like fault injection sessions in order to predict error rates of digital processors. The code emulated upset (CEU) approach allows fault injection in processor memories (caches and register files), while...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2007-08, Vol.54 (4), p.924-928
Main Authors: Valderas, M.G., Peronnard, P.., Lopez Ongil, C., Ecoffet, R.., Bezerra, F., Velazco, R..
Format: Article
Language:English
Subjects:
Circuit faults
Digital
Emulation
Engineering Sciences
Error analysis
Fault injection
fault tolerance
Faults
Field programmable gate arrays
Flip-flops
FPGA emulation
Micro and nanotechnologies
Microelectronics
Particle measurements
Permissible error
Processors
Registers
SEU
Single event transient
Single event upset
Strategy
System testing
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Description
Summary:This paper describes two different but complementary approaches that can be used to perform SEU-like fault injection sessions in order to predict error rates of digital processors. The code emulated upset (CEU) approach allows fault injection in processor memories (caches and register files), while the FPGA autonomous emulation approach allows fault injection in processor flip-flops. Results obtained for a case studied, the LEON processor, illustrate the complementary aspects of proposed strategies.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2007.893871