A Passive Switched-Capacitor Finite-Impulse-Response Equalizer

A passive CMOS switched-capacitor finite-impulse-response equalizer is described. A sampling rate of 200 MS/s is achieved by six time-interleaved channels. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations of the equalizer for a binary or ternary data...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2007-02, Vol.42 (2), p.400-409
Main Authors: Guilar, N.J., Lau, F., Hurst, P.J., Lewis, S.H.
Format: Article
Language:English
Subjects:
Channels
Circuits
Clock drivers
Clocks
CMOS
Communication channels
Consumption
Digital filters
Dissipation
Equalizer
Equalizers
Finite impulse response filter
FIR filter
Intersymbol interference
Parasitic capacitance
Prototypes
Sampling
Sampling methods
switched-capacitor filter
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Summary:A passive CMOS switched-capacitor finite-impulse-response equalizer is described. A sampling rate of 200 MS/s is achieved by six time-interleaved channels. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations of the equalizer for a binary or ternary data signal. The 4-tap equalizer prototype is fully differential. At 200 MS/s, the equalizer dissipates 19.5 mW, which is virtually all consumed by clock drivers, and occupies an active area of 1.3 mm 2 in a 0.35 mum CMOS process
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2006.889378