Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is domin...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2007-12, Vol.54 (6), p.2506-2511
Main Authors: Narasimham, B., Bhuva, B.L., Schrimpf, R.D., Massengill, L.W., Gadlage, M.J., Amusan, O.A., Holman, W.T., Witulski, A.F., Robinson, W.H., Black, J.D., Benedetto, J.M., Eaton, P.H.
Format: Article
Language:English
Subjects:
CMOS
CMOS technology
combinational logic
Cross sections
Digital
DSET
Heavy ions
Integrated circuit technology
Logic
Microelectronics
Position (location)
Pulse circuits
Pulse measurements
pulse-width
SET
SEU
Simulation
single event
single event transient
Single event upset
soft error
Soft errors
Space technology
Space vector pulse width modulation
Strikes
Voltage
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Summary:The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps in the 90-nm process. The increasing probability of longer SET pulses with scaling is a key factor determining combinational logic soft errors in advanced technologies. Mixed mode 3D-TCAD simulations demonstrate that the variation of pulse-width results from the variation in strike location.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2007.910125