Novel Approach to Reduce Source/Drain Series and Contact Resistance in High-Performance UTSOI CMOS Devices Using Selective Electrodeless CoWP or CoB Process

• Published in: IEEE electron device letters 2007-08, Vol.28 (8), p.691-693
• Main Authors: Pan, J., Topol, A., Shao, I., Chun-Yung Sung, Iacoponi, J., Ming-Ren Lin
• Format: Article
• Language: English
• Subjects: Applied sciences; CMOS; CMOS process; CoB; Cobalt; Contact resistance; CoWP; Deposition; Design. Technologies. Operation analysis. Testing; Devices; Dielectric substrates; Drains; electrodeless (E-less); Electronics; Electrons; Exact sciences and technology; fully depleted silicon-on-insulator (FDSOI); Integrated circuits; Leakage current; MOSFETs; Nickel; raised source/drain (RSD); selective metal deposition; Selectivity; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicides; Silicon on insulator technology; Transistors; ultrathin silicon-on-insulator (UTSOI)
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2007.900865

This letter reports a selective metal deposition process using an electrodeless technique for MOSFETs fabricated in an ultrathin silicon-on-insulator (UTSOI) substrate. A layer of metal (CoWP or CoB) is formed on the source and drain nickel and cobalt silicides without depositing on the dielectric spacers. Leakage current information, which is an indication of selectivity of the process, is presented in this letter. The shortest channel length of the UTSOI NMOSFETs is 20 nm, and the SOI thickness is 10 nm. The data show that excellent selectivity is achieved without increasing the leakage current of the transistors.