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Spacer-First Damascene-Gate FinFET Architecture Featuring Stringer-Free Integration
This letter presents a new Damascene-gate FinFET process that inherently suppresses stringers, resulting from gate and spacers patterning. The so-called spacer-first integration scheme relies on the engineering of a hydrogen silsesquioxane layer by electron beam lithography followed by two selective...
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| Published in: | IEEE electron device letters 2007-06, Vol.28 (6), p.523-526 |
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| Main Authors: | , , , , , |
| Format: | Article |
| Language: | English |
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| cited_by | cdi_FETCH-LOGICAL-c416t-8b0f82a971664d04561c288d5821c07caa4c313b2253740963f189937d03d5c63 |
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| cites | cdi_FETCH-LOGICAL-c416t-8b0f82a971664d04561c288d5821c07caa4c313b2253740963f189937d03d5c63 |
| container_end_page | 526 |
| container_issue | 6 |
| container_start_page | 523 |
| container_title | IEEE electron device letters |
| container_volume | 28 |
| creator | Cornu-Fruleux, F. Penaud, J. Dubois, E. Coronel, P. Larrieu, G. Skotnicki, T. |
| description | This letter presents a new Damascene-gate FinFET process that inherently suppresses stringers, resulting from gate and spacers patterning. The so-called spacer-first integration scheme relies on the engineering of a hydrogen silsesquioxane layer by electron beam lithography followed by two selective compartmentalized development steps to successively release the Damascene-gate cavity and the source/drain (S/D) contact regions. In contrast to the existing gate-first and gate-last integration approaches, the resulting FinFET process does not impose any restriction or interdependency on the sizing of the fins, gate, spacers, and S/D regions. A complete morphological and electrical validation is proposed in the particular case of wrap-around self-aligned metallic Schottky S/D contacts. |
| doi_str_mv | 10.1109/LED.2007.897443 |
| format | article |
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The so-called spacer-first integration scheme relies on the engineering of a hydrogen silsesquioxane layer by electron beam lithography followed by two selective compartmentalized development steps to successively release the Damascene-gate cavity and the source/drain (S/D) contact regions. In contrast to the existing gate-first and gate-last integration approaches, the resulting FinFET process does not impose any restriction or interdependency on the sizing of the fins, gate, spacers, and S/D regions. A complete morphological and electrical validation is proposed in the particular case of wrap-around self-aligned metallic Schottky S/D contacts.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2007.897443</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Contact ; Contacts ; Dielectric substrates ; Drains ; Electric contacts ; Electron beam lithography ; Electron beams ; Electronics ; Electrostatics ; Engineering Sciences ; Etching ; Exact sciences and technology ; FinFET ; FinFETs ; Fins ; Gates ; Holes ; Hydrogen ; hydrogen silsesquioxane (HSQ) ; Interfaces ; Lithography ; Microelectronic fabrication (materials and surfaces technology) ; multiple gate ; Schottky barrier ; Schottky barriers ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Spacers ; Surface resistance ; Transistors</subject><ispartof>IEEE electron device letters, 2007-06, Vol.28 (6), p.523-526</ispartof><rights>2007 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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The so-called spacer-first integration scheme relies on the engineering of a hydrogen silsesquioxane layer by electron beam lithography followed by two selective compartmentalized development steps to successively release the Damascene-gate cavity and the source/drain (S/D) contact regions. In contrast to the existing gate-first and gate-last integration approaches, the resulting FinFET process does not impose any restriction or interdependency on the sizing of the fins, gate, spacers, and S/D regions. A complete morphological and electrical validation is proposed in the particular case of wrap-around self-aligned metallic Schottky S/D contacts.</description><subject>Applied sciences</subject><subject>Contact</subject><subject>Contacts</subject><subject>Dielectric substrates</subject><subject>Drains</subject><subject>Electric contacts</subject><subject>Electron beam lithography</subject><subject>Electron beams</subject><subject>Electronics</subject><subject>Electrostatics</subject><subject>Engineering Sciences</subject><subject>Etching</subject><subject>Exact sciences and technology</subject><subject>FinFET</subject><subject>FinFETs</subject><subject>Fins</subject><subject>Gates</subject><subject>Holes</subject><subject>Hydrogen</subject><subject>hydrogen silsesquioxane (HSQ)</subject><subject>Interfaces</subject><subject>Lithography</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>multiple gate</subject><subject>Schottky barrier</subject><subject>Schottky barriers</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Spacers</subject><subject>Surface resistance</subject><subject>Transistors</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><recordid>eNp9kc1rGzEQxUVpIW7acw69LIWG9rDOjL51NEmcBAw9uD0LRdYmCutdV5IL_e-jZUMKPfQ0MPq9p5l5hJwhLBHBXGyur5YUQC21UZyzN2SBQugWhGRvyQIUx5YhyBPyPucnAORc8QXZbg_Oh9SuY8qluXJ7l30YQnvjSmjWcVhf_2hWyT_GEnw5ptoLrtY4PDTbMpVJm0Jo7oYSHpIrcRw-kHed63P4-FJPyc9qc3nbbr7f3F2uNq3nKEur76HT1BmFUvIdcCHRU613QlP0oLxz3DNk95QKpjgYyTrUxjC1A7YTXrJT8m32fXS9PaS4d-mPHV20t6uNnXoAtJ5A4G-s7PnMHtL46xhysftYN-17N4TxmC3jgklpaAW__hdEqZCZOquo6Od_0KfxmIa6sjVIUXOACbqYIZ_GnFPoXidFsFNwtgZnp-DsHFxVfHmxrVm4vktu8DH_lWmNKNTEfZq5GEJ4fea0fq2APQPCypyW</recordid><startdate>20070601</startdate><enddate>20070601</enddate><creator>Cornu-Fruleux, F.</creator><creator>Penaud, J.</creator><creator>Dubois, E.</creator><creator>Coronel, P.</creator><creator>Larrieu, G.</creator><creator>Skotnicki, T.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Microelectronics. Optoelectronics. Solid state devices</topic><topic>Spacers</topic><topic>Surface resistance</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Cornu-Fruleux, F.</creatorcontrib><creatorcontrib>Penaud, J.</creatorcontrib><creatorcontrib>Dubois, E.</creatorcontrib><creatorcontrib>Coronel, P.</creatorcontrib><creatorcontrib>Larrieu, G.</creatorcontrib><creatorcontrib>Skotnicki, T.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) Online</collection><collection>IEEE Electronic Library Online</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Hyper Article en Ligne (HAL)</collection><collection>Hyper Article en Ligne (HAL) (Open Access)</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Cornu-Fruleux, F.</au><au>Penaud, J.</au><au>Dubois, E.</au><au>Coronel, P.</au><au>Larrieu, G.</au><au>Skotnicki, T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Spacer-First Damascene-Gate FinFET Architecture Featuring Stringer-Free Integration</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2007-06-01</date><risdate>2007</risdate><volume>28</volume><issue>6</issue><spage>523</spage><epage>526</epage><pages>523-526</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>This letter presents a new Damascene-gate FinFET process that inherently suppresses stringers, resulting from gate and spacers patterning. The so-called spacer-first integration scheme relies on the engineering of a hydrogen silsesquioxane layer by electron beam lithography followed by two selective compartmentalized development steps to successively release the Damascene-gate cavity and the source/drain (S/D) contact regions. In contrast to the existing gate-first and gate-last integration approaches, the resulting FinFET process does not impose any restriction or interdependency on the sizing of the fins, gate, spacers, and S/D regions. A complete morphological and electrical validation is proposed in the particular case of wrap-around self-aligned metallic Schottky S/D contacts.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/LED.2007.897443</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0001-5157-2277</orcidid><orcidid>https://orcid.org/0000-0001-7573-1201</orcidid><orcidid>https://orcid.org/0000-0002-0347-010X</orcidid><oa>free_for_read</oa></addata></record> |
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| identifier | ISSN: 0741-3106 |
| ispartof | IEEE electron device letters, 2007-06, Vol.28 (6), p.523-526 |
| issn | 0741-3106 1558-0563 |
| language | eng |
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| source | IEEE Xplore (Online service) |
| subjects | Applied sciences Contact Contacts Dielectric substrates Drains Electric contacts Electron beam lithography Electron beams Electronics Electrostatics Engineering Sciences Etching Exact sciences and technology FinFET FinFETs Fins Gates Holes Hydrogen hydrogen silsesquioxane (HSQ) Interfaces Lithography Microelectronic fabrication (materials and surfaces technology) multiple gate Schottky barrier Schottky barriers Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Spacers Surface resistance Transistors |
| title | Spacer-First Damascene-Gate FinFET Architecture Featuring Stringer-Free Integration |
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