Clock-Logic Domino Circuits for High-Speed and Energy-Efficient Microprocessor Pipelines

We present a design methodology for synchronous single-rail domino logic circuits, where inverting and nonmonotonic logic functions can be integrated into a pipeline with almost zero overhead relative to classic domino counterparts. This logic family, called clock-logic (CL) domino, is functionally...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2007-05, Vol.54 (5), p.460-464
Main Authors: Jit-Hung Sung, R., Elliott, D.G.
Format: Article
Language:English
Subjects:
Algorithmic logic unit (ALU)
Circuits
clock skew
Clocks
computer architecture
Delay
Design engineering
digital integrated circuits
dynamic logic
Energy consumption
Energy efficiency
High speed
integrated circuit design
Latches
Logic
Logic circuits
Logic design
Logic functions
low power
Microprocessors
Phases
Pipelines
Reduction
Synchronous
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Summary:We present a design methodology for synchronous single-rail domino logic circuits, where inverting and nonmonotonic logic functions can be integrated into a pipeline with almost zero overhead relative to classic domino counterparts. This logic family, called clock-logic (CL) domino, is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL domino algorithmic logic unit (ALU) at 1 GHz under high skew conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required
ISSN:1549-7747
1057-7130
1558-3791
DOI:10.1109/TCSII.2007.892212