Improved High Temperature Retention for Charge-Trapping Memory by Using Double Quantum Barriers

We have fabricated the [TaN-Ir 3 Si]-HfAlO-LaAlO 3 -Hf 0.3 O 0.5 N 0.2 -HfAlO-SiO 2 -Si double quantum-barrier charge- trapping memory device. Under fast 100 mus and low plusmn8 V program/erase (P/E) condition, an initial memory window of 2.6 V and good extrapolated ten-year retention window of 1.9...

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Bibliographic Details
Published in:IEEE electron device letters 2008-04, Vol.29 (4), p.386-388
Main Authors: Yang, H.J., Chin, A., Lin, S.H., Yeh, F.S., McAlister, S.P.
Format: Article
Language:English
Subjects:
Applied sciences
Atherosclerosis
Barriers
Carrier confinement
Current measurement
Data storage
Decay
Design. Technologies. Operation analysis. Testing
Devices
Electronics
Erase
Exact sciences and technology
Extrapolation
Hafnium
high- kappa
Integrated circuits
Integrated circuits by function (including memories and processors)
Leakage current
Magnetic and optical mass memories
Memory devices
MONOS devices
Nonvolatile memory
program
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Senior members
Storage and reproduction of information
Temperature
Trapping
Tunneling
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Summary:We have fabricated the [TaN-Ir 3 Si]-HfAlO-LaAlO 3 -Hf 0.3 O 0.5 N 0.2 -HfAlO-SiO 2 -Si double quantum-barrier charge- trapping memory device. Under fast 100 mus and low plusmn8 V program/erase (P/E) condition, an initial memory window of 2.6 V and good extrapolated ten-year retention window of 1.9 V are achieved at 125degC. Very small P/E retention decays of 64/22 mV/dec at 125degC are measured due to double quantum barriers to confine the charges in deep-trapping-energy Hf 0.3 O 0.5 N 0.2 well.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2008.917811