A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit

• Published in: IEEE journal of solid-state circuits 2008-05, Vol.43 (5), p.1101-1118
• Main Authors: Afsahi, A., Rael, J.J., Behzad, A., Hung-Ming Chien, Pan, M., Au, S., Ojo, A., Lee, C.P., Anand, S.B., Chien, K., Wu, S., Roufoogaran, R., Zolfaghari, A., Leete, J.C., Long Tran, Carter, K.A., Nariman, M., Yeung, K.W.-K., Morton, W., Gonikberg, M., Seth, M., Forbes, M., Pattin, J., Gutierrez, L., Ranganathan, S., Ning Li, Blecker, E., Lin, J., Kwan, T., Zhu, R., Chambers, M., Rofougaran, M., Rofougaran, A., Trachewsky, J., Van Rooyen, P.
• Format: Article
• Language: English
• Subjects: Adaptive control; auto-calibrated radio; beamforming; cartesian phase shifter; CMOS; CMOS analog integrated circuits; Energy consumption; frequency synthesizers; Gold; Jacobian matrices; low-power WLAN SOC; maximum ratio combiner (MRC); mixed analog-digital integrated circuits; multiple-antenna system; phase shifter; Phase shifters; phased array; Phased arrays; Radio frequency; Receivers; single weight combiner (SWC); Transceivers; Wireless LAN
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2008.920338

A low-power 802.11abg SoC which achieves the best reported sensitivity as well as lowest reported power consumption and utilizes an extensive array of auto calibrations is reported. This SoC utilizes a two-antenna array receiver to build a single weight combiner (SWC) system. A new signal-path Cartesian phase generation and combination technique is proposed that shifts the RF signal in 22.5deg phase steps. A 3 dB improvement in received SNR is achieved in comparison to the single path receiver. The radio and AFE occupy 10 mm 2 of area in a digital 0.13 mum CMOS process of which 0.29 mm 2 is occupied by the SWC RF receiver. The radio+AFE consume 85 mW of power in active Rx mode of which 30 mW is utilized by the SWC RF front-end.