Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire

An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around t...

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Bibliographic Details
Published in:IEEE electron device letters 2008-01, Vol.29 (1), p.102-105
Main Authors: IM, Maesoon, HAN, Jin-Woo, YUN CHANG PARK, HEE MOK LEE, CHOI, Yang-Kyu, LEE, Hyunjin, YU, Lee-Eun, KIM, Sungho, KIM, Chang-Hoon, SANG CHEOL JEON, KWANG HEE KIM, GI SUNG LEE, JAE SUB OH
Format: Article
Language:English
Subjects:
Applied sciences
CMOS
Consumer electronics
Crystallization
Delay effects
Design. Technologies. Operation analysis. Testing
Devices
Dielectrics
Electronics
Energy consumption
Exact sciences and technology
Grain boundaries
Grain size
Integrated circuits
Memory
multiple gate
Nanocomposites
Nanomaterials
nanoscale
Nanoscale devices
Nanostructure
nanowire
Nanowires
Semiconductor devices
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Switching
Thin film transistors
Thin films
thin-film transistor (TFT)
Transistors
vertical integration
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Description
Summary:An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2007.911982