Dominant Layer for Stress-Induced Positive Charges in Hf-Based Gate Stacks

Positive charges in Hf-based gate stacks play an important role in the negative bias temperature instability of pMOSFETs, and their suppression is a pressing issue. The location of positive charges is not clear, and central to this letter is determining which layer of the stack dominates positive ch...

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Bibliographic Details
Published in:IEEE electron device letters 2008-12, Vol.29 (12), p.1360-1363
Main Authors: Zhang, J.F., Mo Huai Chang, Zhigang Ji, Lin Lin, Ferain, I., Groeseneken, G., Pantisano, L., De Gendt, S., Heyns, M.M.
Format: Article
Language:English
Subjects:
Applied sciences
Charging
Dielectric substrates
Dielectrics
Electron traps
Electronics
Exact sciences and technology
Gates
Hafnium
Hf silicates
high- k gate dielectric
Instability
Interface states
MOSFETs
Negative bias temperature instability
negative bias temperature instability (NBTI)
Niobium compounds
positive charges
Pressing
Pulse measurements
reliability
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Solvents
spatial distribution
Stacks
Titanium compounds
Transistors
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Summary:Positive charges in Hf-based gate stacks play an important role in the negative bias temperature instability of pMOSFETs, and their suppression is a pressing issue. The location of positive charges is not clear, and central to this letter is determining which layer of the stack dominates positive charging. The results clearly show that positive charges are dominated by the interfacial layer (IL) and that they do not pile up at the HfSiON/IL interface. The results support the assumption that positive charges are located close to the IL/substrate interface. Unlike electron trapping that reduces rapidly for thinner Hf dielectric layer, positive charges cannot be reduced by using a thinner HfSiON film.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2008.2006288