High-Performance Low-Power Selective Precharge Schemes for Address Decoders

Two novel address decoder schemes using selective precharging are presented and analyzed in this paper. These schemes, the AND-NOR and sense amplifier (sense-amp) decoders, are compared to the NOR decoder using 90-nm CMOS technology. The sense-amp decoder dissipates between 29.5% and 50.1% and the A...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2008-09, Vol.55 (9), p.917-921
Main Authors: Turi, M.A., Delgado-Frias, J.G.
Format: Article
Language:English
Subjects:
Address decoder
Circuit simulation
Circuits
Clocks
CMOS
CMOS technology
Computational modeling
Decoders
Decoding
Delay
Dissipation
high performance
Performance analysis
Power generation
Random access memory
selective precharge
sense amplifier (Sense-Amp)
Sense amplifiers
Synchronization
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Summary:Two novel address decoder schemes using selective precharging are presented and analyzed in this paper. These schemes, the AND-NOR and sense amplifier (sense-amp) decoders, are compared to the NOR decoder using 90-nm CMOS technology. The sense-amp decoder dissipates between 29.5% and 50.1% and the AND-NOR decoder dissipates between 73.7% and 104.4% of the energy dissipated by the NOR decoder. The delay of the Sense-Amp decoder is 69.2% and the delay of the AND-NOR decoder is 80.8% of the nor decoder delay.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2008.923435