A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-[Formula Omitted]m CMOS Technology

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2009-05, Vol.17 (5), p.688
Main Authors: Kao, Min-Sheng, Wu, Jen-Ming, Lin, Chih-Hsing, Chen, Fan-Ta, Chiu, Ching-Te, Hsu, S.S.H
Format: Article
Language:English
Online Access:Get full text
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2009.2016726