Efficient Hierarchical Motion Estimation Algorithm and Its VLSI Architecture

This paper addresses the development and hardware implementation of an efficient hierarchical motion estimation algorithm, HMEA, using multiresolution frames to reduce the computational complexity. Excellent estimation performance is ensured using an averaging filter to downsample the original image...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2008-10, Vol.16 (10), p.1385-1398
Main Authors: WU, Bing-Fei, PENG, Hsin-Yuan, YU, Tung-Lung
Format: Article
Language:English
Subjects:
Algorithms
Applied sciences
Architecture
Chaos
Computer architecture
Control engineering
Design. Technologies. Operation analysis. Testing
Electronics
Encoding
Exact sciences and technology
Filters
Hardware
Hierarchical
Integrated circuits
Integrated circuits by function (including memories and processors)
Mathematical analysis
Motion estimation
multiresolution
Searching
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Studies
Transform coding
Vectors (mathematics)
Very large scale integration
Video compression
VLSI
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Summary:This paper addresses the development and hardware implementation of an efficient hierarchical motion estimation algorithm, HMEA, using multiresolution frames to reduce the computational complexity. Excellent estimation performance is ensured using an averaging filter to downsample the original image. At the smallest resolution, the least two motion vector candidates are selected using a full-search block matching algorithm. At the middle level, these two candidate motion vectors are employed as the center points for small range local searches. Then, at the original resolution, the final motion vector is obtained by performing a local search around the single candidate from the middle level. HMEA exhibits regular data flow and is suitable for hardware implementation. An efficient VLSI architecture that includes an averaging filter to downsample the image and two 2-D semisystolic processing element arrays to determine the sum of absolute difference in pipeline is also presented. Simulation results indicate that HMEA is more area-efficient and faster than many full-search and multiresolution architectures while maintaining high video quality. This architecture with 59K gates and 1393 bytes of RAM is implemented for a search range of [ -16.0, +15.5].
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2008.2000526