Impacts of Poly-Si Nanowire Shape on Gate-All-Around Flash Memory With Hybrid Trap Layer

• Published in: IEEE electron device letters 2011-10, Vol.32 (10), p.1382-1384
• Main Authors: CHEN, Hung-Bin, WU, Yung-Chun, YANG, Chao-Kan, CHEN, Lun-Chun, CHIANG, Ji-Hong, CHANG, Chun-Yen
• Format: Article
• Language: English
• Subjects: Applied sciences; Cross-disciplinary physics: materials science; rheology; Design. Technologies. Operation analysis. Testing; Devices; Dielectric strength; Electric breakdown; Electrodes; Electronics; Exact sciences and technology; Flash memory; Flash memory (computers); gate-all-around (GAA); Integrated circuits; Integrated circuits by function (including memories and processors); Logic gates; Materials science; Nanocomposites; Nanomaterials; Nanoscale materials and structures: fabrication and characterization; Nanostructure; nanowire (NW); Nanowires; Oxides; Physics; Quantum wires; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Shape; Silicon; Thin film transistors; thin-film transistor (TFT); Transistors
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2011.2161257

This letter demonstrates the shape effect of suspended poly-Si nanowires (NWs) on gate-all-around TFT Flash memory. The NWs are bent into a bimodal shape by process-induced strain. The proposed dual-gate (DG) and single-gate (SG) electrodes are located on the twin peaks and single valley of the bimodal shape of the NWs. The DG structure has better program/erase characteristics and reliability than the SG structure owing to the impact of the bent NWs on the dielectric strength of tunnel oxide. Moreover, incorporation of the hybrid trap layer in the DG device yields a long retention time, with only 17% charge loss over ten years.