Clock Distribution Networks in 3-D Integrated Systems

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2011-12, Vol.19 (12), p.2256-2266
• Main Authors: Pavlidis, V. F., Savidis, I., Friedman, E. G.
• Format: Article
• Language: English
• Subjects: 3-D clock characterization; 3-D clock distribution; 3-D clock modeling; 3-D synchronization; Applied sciences; Circuits; Clocks; Delay; Design engineering; Design. Technologies. Operation analysis. Testing; Driver circuits; Electronics; Exact sciences and technology; Integrated circuit interconnections; Integrated circuits; Network topologies; Network topology; Networks; Planes; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Studies; Synchronization; Testing, measurement, noise and reliability; Three dimensional; Topology; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2010.2073724

3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Good agreement is shown between the modeled and experimental results of a 3-D test circuit composed of three device planes. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew, clock delay, signal slew, and power dissipation measurements for the different clock topologies are also provided. The measurements suggest that each topology provides certain advantages and disadvantages in terms of different performance criteria. The proper choice, consequently, of a clock distribution network is not dictated by a single design objective but rather by the overall 3-D system design requirements including availability of resources and number of bonded planes.