A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs

• Published in: IEEE journal of solid-state circuits 2005-11, Vol.40 (11), p.2246-2264
• Main Authors: de la Rosa, J.M., Escalera, S., Perez-Verdu, B., Medeiro, F., Guerra, O., del Rio, R., Rodriguez-Vazquez, A.
• Format: Article
• Language: English
• Subjects: Analog-to-digital conversion; Applied sciences; Automotive electronics; Automotive engineering; Capacitors; Circuit properties; Circuit topology; Delta-sigma modulation; Design. Technologies. Operation analysis. Testing; Dielectric, amorphous and glass solid devices; Electric, optical and optoelectronic circuits; Electronics; Exact sciences and technology; Integrated circuits; Integrated optoelectronics. Optoelectronic circuits; Miscellaneous; mixed analog-digital integrated circuits; Modulation coding; Optical and optoelectronic circuits; Power dissipation; sampled data circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sensor phenomena and characterization; sigma-delta modulation; Temperature distribution; Temperature sensors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2005.857356

This paper describes a 0.35-/spl mu/m CMOS chopper-stabilized switched-capacitor 2-1 cascade /spl Sigma//spl Delta/ modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values (/spl times/0.5,/spl times/1,/spl times/2, and /spl times/4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40/spl deg/C to 175/spl deg/C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm/sup 2/ silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution /spl Sigma//spl Delta/ modulators.