Low-Power 10-Gb/s Transmitter for High-Speed Graphic DRAMs Using 0.18- [Formula Omitted] CMOS Technology

• Published in: IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2011-12, Vol.58 (12), p.921
• Main Authors: Song, Jun-Yong, Kwon, Oh-Kyong
• Format: Article
• Language: English
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2011.2172716

This brief presents a 10-Gb/s transmitter using a low-power one-stage 8:1 multiplexer. In the proposed transmitter, a differential current-steering output driver with a multiphase multiplexer architecture is used to alleviate speed limitations of the DRAM process. The current-steering output driver reduces the required output swing and increases the bandwidth of the multiplexer. The proposed multiplexer accomplishes not only high-speed operation but also low power dissipation by using a pseudo-nMOS configuration with one-stacked switches and reducing the short-circuit current of the gate driver in the multiplexer. The prototype of the transmitter using a 0.18- [Formula Omitted] CMOS technology achieves the power efficiency of 5.69 mW/Gb/s at the data rate of 10 Gb/s.