Wafer-Testing of Optoelectonic-Gigascale CMOS Integrated Circuits

Gigascale integration (GSI) chips with high bandwidth, integrated optoelectronics (OE), and photonic components are an emerging technology. In this paper, we present the prospects and opportunities for wafer-testing of chips with electrical and optical I/O interconnects. The issues and requirements...

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Bibliographic Details
Published in:IEEE journal of selected topics in quantum electronics 2011-05, Vol.17 (3), p.659-670
Main Authors: Thacker, H D, Ogunsola, O O, Muler, A V, Meindl, J D
Format: Article
Language:English
Subjects:
Adaptive optics
Chips
CMOS
CMOS photonic testing
compliant probe
Contact
Electric contacts
Integrated circuits
Integrated optics
Microelectromechanical systems
microelectromechanical systems (MEMS) probe
optical I/O
Optical imaging
Optical receivers
Optical sensors
optoelectronic (OE) testing
Optoelectronics
Probes
Quantum electronics
Testing
through-silicon via (TSV)
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Description
Summary:Gigascale integration (GSI) chips with high bandwidth, integrated optoelectronics (OE), and photonic components are an emerging technology. In this paper, we present the prospects and opportunities for wafer-testing of chips with electrical and optical I/O interconnects. The issues and requirements of testing OE-GSI ICs during high-volume manufacturing are identified and discussed. Two probe substrate technologies based on microelectromechanical systems (MEMS) for simultaneously interfacing with a multitude of surface-normal optical I/Os and high-density electrical I/Os are detailed. The first probe substrate comprises vertically compliant probes for contacting electrical I/Os and grating-in-waveguide I/Os for optical probing. The second MEMS probe module uses microsockets and through-substrate interconnects to contact pillar-shaped electrical and optical I/Os and to redistribute signals, respectively.
ISSN:1077-260X
1558-4542
DOI:10.1109/JSTQE.2010.2089431