Prediction and Comparison of High-Performance On-Chip Global Interconnection

As process technology scales, numerous interconnect schemes have been proposed to mitigate the performance degradation caused by the scaling of on-chip global wires. In this paper, we review current on-chip global interconnect structures and develop simple models to analyze their architecture-level...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2011-07, Vol.19 (7), p.1154-1166
Main Authors: Yulei Zhang, Xiang Hu, Deutsch, A., Engin, A. E., Buckwalter, J. F., Chung-Kuan Cheng
Format: Article
Language:English
Subjects:
Applied sciences
Categories
Degradation
Delay
Design engineering
Design. Technologies. Operation analysis. Testing
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Equalization
Exact sciences and technology
Integrated circuits
Interconnect
Interconnection
Intersymbol interference
On-chip global interconnect
passive equalization
Performance analysis
performance prediction
Power system interconnection
Power transmission lines
Reinforced concrete
Repeaters
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal integrity
System-on-a-chip
Throughput
transmission line
Very large scale integration
Wire
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Summary:As process technology scales, numerous interconnect schemes have been proposed to mitigate the performance degradation caused by the scaling of on-chip global wires. In this paper, we review current on-chip global interconnect structures and develop simple models to analyze their architecture-level performance. We propose a general framework to design and optimize a new category of global interconnect based on on-chip transmission line (T-line) technology. We perform a group of experiments using six different global interconnection structures to discover their differences in terms of latency, energy per bit, throughput, area, and signal integrity over several technology nodes. Our results show that T-line structures have the potential to outperform conventional repeated RC wires at future technology nodes to achieve higher performance while using less power and improving the reliability of wire communication. Our results also show that on-chip equalization is helpful to improve throughput, signal integrity, and power efficiency.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2010.2047415