A 550-[Formula Omitted] 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction

A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible hardware overhead. The redundant decision cycles be...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2011-08, Vol.46 (8), p.1881
Main Authors: Cho, Sang-Hyun, Lee, Chang-Kyo, Kwon, Jong-Kee, Ryu, Seung-Tak
Format: Article
Language:English
Online Access:Get full text
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Summary:A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible hardware overhead. The redundant decision cycles between stages reconfigure the capacitor connection of the DAC. These redundancies guarantee 10-b linearity under 4-b-accurate DAC settling in the MSB decision and the optimally designed ADC enhances the conversion speed by 37%. A prototype ADC was implemented in a CMOS 0.13-[Formula Omitted] technology. The chip consumes 550 [Formula Omitted] and achieves a 50.6-dB SNDR at 40 MS/s under a 1.2-V supply. The figure-of-merit (FOM) is 50 fJ/conversion-step.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2011.2151450