A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2005-02, Vol.13 (2), p.191-200
• Main Authors: Centurelli, F., Golfarelli, A., Guinea, J., Masini, L., Morigi, D., Pozzoni, M., Scotti, G., Trifiletti, A.
• Format: Article
• Language: English
• Subjects: 10 Gigabit Ethernet; Amplifiers; Applied sciences; BiCMOS integrated circuits; Circuit properties; Clocks; Communications; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Frequency; Germanium silicon alloys; Integrated circuits; Jitter; mixed-signal; optical; Oscillators, resonators, synthetizers; Phase locked loops; phase-locked loop; SDH STM-64; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SiGe integrated circuits; Signal convertors; Silicon germanium; SONET; SONET OC-192; Synchronous digital hierarchy; Tracking loops
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2004.840784

A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data recovery (CDR) features a 20-mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize clock phase margin (CPM) and a dual-loop phase-locked loop (PLL) architecture with external reference clock. A novel phase detector topology featuring a transition density factor compensation loop has been exploited to minimize jitter. Power consumption is 480 mW and 780 mW, respectively, for the two ICs, from 3.3-V and 2.5-V power supplies