An efficient merging scheme for prescribed skew clock routing

In ultra-deep submicron very large-scale integration (VLSI) designs, clock network layout plays an increasingly important role on determining circuit quality indicated by timing, power consumption, cost, power-supply noise, and tolerance to process variations. In this brief, a new merging scheme is...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2005-06, Vol.13 (6), p.750-754
Main Authors: Chaturvedi, R., Jiang Hu
Format: Article
Language:English
Subjects:
Applied sciences
Circuit noise
Clocks
Costs
design automation
Design. Technologies. Operation analysis. Testing
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Energy consumption
Exact sciences and technology
Integrated circuits
Large scale integration
Merging
Noise reduction
Routing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Timing
Very large scale integration
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Description
Summary:In ultra-deep submicron very large-scale integration (VLSI) designs, clock network layout plays an increasingly important role on determining circuit quality indicated by timing, power consumption, cost, power-supply noise, and tolerance to process variations. In this brief, a new merging scheme is proposed for prescribed nonzero skew routings which are useful in reducing clock cycle time, suppressing power-supply noise, and improving tolerance to process variations. This technique is simple and easy to implement for practical applications. Experimental results on benchmark circuits with both buffered and unbuffered routings exhibit large improvement on wirelength and buffer cost compared with other existing works.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2005.848821